A digital decimation filter applied to audio Sigma-Delta ADC is designed. The filter adopts the design of multi-stage and multi-rate down sampling structure, in-band ripple of decimation filter is less than 0.06 dB overall, bandwidth is 21.6 kHz, minimum working frequency is 10 MHz. Through the innovation of filter hardware architecture design, it effectively reduces the filter circuit area and power consumption. Chip test results show that the SNR is above 87.2 dB when processing PDM signals is at the down sampling rate of 64, 4 order Sigma-Delta modulation. Designed in SMIC’s 0.13 μm CMOS process, the decimation filter area is 0.146 mm². Filter area is reduced by 58%, and power consumption is reduced by over 60% compared with the same type decimation filters.